CDB8422
5. JUMPER SETTINGS
JMP
J20
J11
J8
J13
J17
J4
J9
J14
J18
J23
J31
J21
J29
LABEL
[No Label]
DC0
DC1
DC2
DC3
[No Label]
[No Label]
CS8406/TX
DIFF IN SEL
PURPOSE
Selects voltage source for the
CDB8422
Bypasses optical S/PDIF input DC
coupling capacitor
Selects S/PDIF input source to
receiver input pins of CS8422
Selects XTI clock source for
CS8422
Selects S/PDIF signal source for
J27 and J28
Connects AES3/EBU signal from
J19 to receiver input pins of
CS8422
POSITION
1-2
*2 - 3
SHUNTED
*OPEN
*1 - 2
2-3
1-2
*3 - 4
5-6
1-2
*2 - 3
*RXP0/RXN0
RXP1/RXN1
FUNCTION SELECTED
Voltage source is USB connection (J37).
Voltage source is +5 V binding post (J2).
0.01 μF series capacitor is shorted.
0.01 μF series capacitor in optical input path.
Optical S/PDIF input selected.
Coaxial S/PDIF input selected.
Crystal Y2 selected.
Oscillator Y1 selected.
MCLK from header J22 selected.
GPO2 S/PDIF pass through from CS8422 selected.
CS8406 S/PDIF output selected.
RXP0/RXN0 input pair selected.
RXP1/RXN1 input pair selected.
Table 7. Jumper Settings
Note:
Note:
All settings denoted by an asterisk (*) are the Default Factory Settings.
If a S/PDIF source is connected to the board, the AES3/EBU jumpers (J21 and J29) should be unpop-
ulated to ensure proper operation. If an AES3/EBU source is connected to the board, the S/PDIF
jumpers (J4, J9, J14, and J18) should be unpopulated to ensure proper operation.
6. LEDS
LED
D2
D3
D4
D8
D14
D15
LABEL
GPO2/NV_RERR
GPO0/V_AUDIO
GPO1/SRC_UNLOCK
USB PRESENT
DONE
INIT
Hardware Mode
NV/RERR (CS8422 pin 9)
V/AUDIO (CS8422 pin 10)
SRC_UNLOCK (CS8422 pin 30)
USB power indicator
FPGA programming finished
FPGA programming initialized
Software Mode
GPO2 (CS8422 pin 18)
GPO0 (CS8422 pin 16)
GPO1 (CS8422 pin 17)
USB power indicator
FPGA programming finished
FPGA programming initialized
Table 8. LEDs
DS692DB2
29
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